Conventional LTPS (low-temperature-polycrystalline-silicon) shifting registers are comprised of inverters and transmission gates, and typically have two latches. The latches are used to latch output signals and switches of the transmission gates are used to achieve delay and shift of the signals.
FIG. 1 shows a conventional shifting register that is mainly comprised of two D-triggers, and has D as the input, Q as the output, reset as the reset, and clk_ and clk as two (mutually) inverted clock signals with its principle of operation being that, when a clock turns on a first D-trigger, a level signal inputted from the previous stage shifting register enters into the first D-trigger, and cannot enter into a second D-trigger as the transmission gate at the front end of the second D-trigger is off at that time, and with the arrival of a next clock, the input of the first D-trigger is turned off while the first D-trigger latches the input signal, at the same time the second D-triggers is turned on and the input signal enters into the second D-trigger and is outputted. Thus a shift-operation from the previous stage shifting register to the next stage shifting register is achieved for the signal. For achieving a D-trigger, two transmission gates, one inverter and one NAND gate are required, while two D-triggers are required for one shifting register. Although the conventional shifting registers are deemed classic, they are not favorable for achieving a panel narrow frame as more gate circuits have been used, circuit composition are too complicated and bigger layout space is needed.